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Evaluation of scalable gate architecture components for Si/SiGe spin qubits - Single-shot spin readout, enhanced charge sensing and noise spectroscopy

URN to cite this document:
urn:nbn:de:bvb:355-epub-583587
DOI to cite this document:
10.5283/epub.58358
Schmidbauer, Andreas
Date of publication of this fulltext: 03 Jun 2024 07:51


Abstract (English)

The main objective of this thesis was the investigation of components for gate-defined Si/SiGe spin qubit devices, amid the currently ongoing scaling from demonstrator spin qubit devices to large-scale fault-tolerant quantum computing. We focused in particular on the sensor of such a spin qubit device which is a pivotal component of a quantum processor. Not only is fast and high fidelity ...

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Translation of the abstract (German)

Das Hauptziel dieser Arbeit war die Untersuchung von Komponenten für gatter-definierte Si/SiGe-Spin-Qubit-Bauelemente inmitten der derzeit stattfindenden Skalierung von Prototypen-Spin-Qubit-Bauelementen zu groß angelegten fehlertoleranten Quantencomputern. Wir konzentrierten uns insbesondere auf den Sensor eines solchen Spin-Qubit-Bauelements, der eine zentrale Komponente eines Quantenprozessors ...

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