![]() | License: Creative Commons Attribution 4.0 PDF - Accepted Version (11MB) |
- URN to cite this document:
- urn:nbn:de:bvb:355-epub-766533
- DOI to cite this document:
- 10.5283/epub.76653
Item type: | Thesis of the University of Regensburg (PhD) |
---|---|
Open Access Type: | Primary Publication |
Date: | 12 May 2025 |
Referee: | Prof. Dr. Dominique Bougeard |
Date of exam: | 5 May 2025 |
Institutions: | Physics > Institute of Experimental and Applied Physics Physics > Institute of Experimental and Applied Physics > Chair Professor Huber > Group Dominique Bougeard |
Keywords: | Si/SiGe spin qubit, device architecture building blocks, silicon, qubit, industrial fabrication, biased cooling, field-effect stack, heterostructure, asymmetric sensing dot, charge sensing, quantum computing |
Dewey Decimal Classification: | 500 Science > 530 Physics |
Status: | Published |
Refereed: | Yes, this version has been refereed |
Created at the University of Regensburg: | Yes |
Item ID: | 76653 |
Abstract (English)
Scalability of the qubit systems remains the central challenge in quantum computing, requiring a shift from proof-of-principle implementations to providing a route towards large-scale systems with millions of qubits to enable fault-tolerant computing. This thesis contributes to this effort by addressing building blocks for scalable Si/SiGe spin qubit device architectures. We first present a ...

Abstract (English)
Scalability of the qubit systems remains the central challenge in quantum computing, requiring a shift from proof-of-principle implementations to providing a route towards large-scale systems with millions of qubits to enable fault-tolerant computing. This thesis contributes to this effort by addressing building blocks for scalable Si/SiGe spin qubit device architectures.
We first present a detailed analysis of five undoped field-effect stacks, which serve as the foundation for realizing various quantum circuits in semiconductor heterostructures, including semiconductor spin qubits. We examine the correlation between transport properties and layer stack properties as well as fabrication details. A comparison of the five field-effect stacks underscores that, although all represent state-of-the-art designs for field-effect applications, they display significant variation in their transport properties. A thorough understanding of field-effect stack properties is therefore crucial for further optimization and tailoring to specific applications. In particular for spin qubit applications, a comprehensive understanding of impurities in the field-effect stack and the disorder potential fluctuations they induce in the quantum well is essential. These factors play a decisive role in the precise control of charging energies, the position and shape of quantum dots, the occurrence of disruptive disorder dots, and the sources of charge noise. Especially in terms of scalability, achieving a high degree of uniformity in field-effect stack properties is essential, as the focus shifts from operating a few qubits at selected locations to integrating many qubits across large-scale architectures.
Building on this, we examine the effect of biased cooling on three selected field-effect stacks from the batch previously studied, an effect that has not yet been considered in undoped Si/SiGe. At operation temperature, biased cooling induces a static electric field within the field-effect stack, resulting from charge reconfiguration at the semiconductor/heterostructure interface at temperatures preceding heterostructure freeze-out. As a result, the field-effect tunable range of the electron density can be deterministically shifted, while the two-dimensional electron gas quality markers, such as electron mobility and the temporal stability of the two-dimensional electron gas density, remain unaffected. Moreover, we develop an empirical model describing the biased cooling effect, which is anticipated to be transferable to any undoped semiconductor heterostructure. With its ability to shift the operation window of individual gates and engineer trapped charges at the dielectric/heterostructure interface, the biased cooling effect offers diverse application possibilities in qubit devices.
Turning to the building block of qubit readout, we introduce a new proximal charge sensor concept tailored for the baseband approach, the asymmetric sensing dot. This concept exploits an asymmetrical capacitive coupling between the sensor dot and its reservoirs, enabling a drastically increased output signal compared to conventional sensor dots, and is predestined to incorporate classical electronics of the readout circuitry on chip. We successfully implemented the asymmetric sensing dot concept in two double quantum dot devices on two material platforms, undoped Si/SiGe and doped GaAs/(Al,Ga)As, demonstrating a drain capacitance reduction by factors of 12 and 13 compared to conventional sensor dot operation, respectively. This underscores the adaptability of the asymmetric sensing dot concept and highlights its equal efficiency across different material platforms. Moreover, we achieved charge sensing operation with the asymmetric sensing dot on a double quantum dot, obtaining a large output voltage swing of 3 mV. The significantly enhanced output signal establishes the asymmetric sensing dot as a promising candidate for advancing the performance of the baseband readout approach in the context of scalable quantum computing.
As the last key aspect of this work, we present one of the first devices fabricated in an industrial setting at Infineon Technologies Dresden’s 200 mm production line as part of the QUASAR collaboration, the industrial demonstrator device. It showcases its ability to efficiently tune a quantum dot to the last electron, forming the foundation for spin qubits, while at the same time enabling state-of-the-art charge sensing for reliable readout of the electronic state. The tuning process of the industrial demonstrator device was remarkably straightforward, showcasing state-of-the-art charge noise, excellent stability, and high reproducibility across cool-downs and setups. Additionally, we perform magnetospectroscopy measurements to gain access to the spin configuration in the few-electron regime as a function of the magnetic field and provide an estimate of a lower bound on the valley splitting, a crucial parameter for qubit operation. The industrial demonstrator device demonstrates the compatibility of heterostructure-based spin qubit devices with industrial CMOS technology, highlighting the potential of Si/SiGe spin qubits for rapid scalability and seamless integration of electronics on the same chip.
Translation of the abstract (German)
In dieser Dissertation werden Komponenten für skalierbare Si/SiGe basierte Spin-Qubit-Prozessorarchitekturen untersucht, beginnend mit gatter-gesteuerten undotierten Halbleiter-Feldeffektbauteilen als Grundlage dieser Qubit-Systeme und der Korrelation ihrer Schichtaufbauten und Herstellungsdetails mit ihren Transporteigenschaften. Anschließend wird der Biased Cooling Effekt an diesen Bauteilen ...

Translation of the abstract (German)
In dieser Dissertation werden Komponenten für skalierbare Si/SiGe basierte Spin-Qubit-Prozessorarchitekturen untersucht, beginnend mit gatter-gesteuerten undotierten Halbleiter-Feldeffektbauteilen als Grundlage dieser Qubit-Systeme und der Korrelation ihrer Schichtaufbauten und Herstellungsdetails mit ihren Transporteigenschaften. Anschließend wird der Biased Cooling Effekt an diesen Bauteilen untersucht, der eng mit einem präzisen Verständnis der Elektrostatik insbesondere von Ladungen an der Grenzfläche zwischen Heterostruktur und Dielektrikum zusammenhängt. Als weitere wichtige Komponente wird ein neues Sensordesign für die Qubit-Auslese mit verbessertem Ausgabesignal präsentiert. Abgerundet wird die Arbeit mit der Untersuchung eines der ersten Qubit-Bauteile, welches in einer industriellen Fertigungslinie innerhalb des nationalen Forschungskonsortiums QUASAR gefertigt wurde.
Metadata last modified: 12 May 2025 04:36